MPMC UNIT-1 Interrupts of 8086

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     REGULATION /BRANCH :R16/R18  ECE/EEE

                                      UNIT-I

Interrupts of 8086

While the CPU is executing a program, an ‘interrupt’ breaks the normal sequence of execution of instructions, diverts its execution to some other program called Interrupt Service Routine (ISR). After executing ISR, the control is transferred back again to the main program which was being executed at the time of interruption.

 INTERRUPT CYCLE OF 8086/8088

There are two types of interrupts.

a)External interrupt- an external device or a signal interrupts the processor from outside or, i.e, the interrupt is generated outside the processor, for example, a keyboard interrupt.

 In 8086, there are two interrupt pins, viz. NMI and INTR.

1)The NMI is a non maskable interrupt input pin which means that any interrupt request at NMI input cannot be masked or disabled by any means. Interrupt is processed in the same way as the INTR interrupt. Interrupt type of the NMI is 2, i.e. the address of the NMI processing routine is stored in location 0008h. This interrupt has higher priority than the maskable interrupt.

 2)The INTR interrupt, however, may be masked using the Interrupt Flag (IF), The INTR. further, is of 256 types. It is a maskable hardware interrupt. The interrupt can be enabled/disabled using STI/CLI instructions or using more complicated method of updating the FLAGS register with the help of the POPF instruction.

b)Internal interrupt-It is generated internally by the processor circuit, or by the execution of an interrupt instruction.

Eg: divide by zero interrupt, overflow interrupt, interrupts due to INT instructions, etc.

When an interrupt occurs, the processor stores FLAGS register into stack, disables further interrupts, fetches from the bus one byte representing interrupt type, and jumps to interrupt processing routine address of which is stored in location 4 X <interrupt type>. Interrupt processing routine should return with the IRET instruction.

The INTR types are from 00 to FFH(or 00 to 255). If more than one type of INTR interrupt occurs at a time, then an external chip called programmable interrupt controller is required to handle them.

Eg: INT <interrupt number>INT 02H Vector Address is  4x02=0008h 

At the end of each instruction cycle 8086 checks to see if there is any interrupt request. 

If so, 8086 responds to the interrupt by performing series of actions

v It decrements stack pointer by 2 and pushes the flag register on the stack.

v It disables the INTR interrupt input by clearing the interrupt flag in the flag register.

v It resets the trap flag in the flag register.

v It decrements stack pointer by 2 and pushes the current CS register contents onto the stack.

v It decrements stack pointer by 2 and pushes the current instruction pointer contents on the stack.

v It does an indirect far jump at the start of the procedure by loading the CS and IP values for the start of the interrupt service routine (ISR).

v An IRET instruction at the end of the interrupt service procedure       returns execution to the main program

 

Interrupt Vector Table

In an 8086 system the first 1 Kbyte of memory from 00000H(0000:0000)  to 03FFH(0000:03FF)  is reserved for storing the starting addresses of interrupt service routines.

This block of memory is often called the interrupt vector table or the interrupt pointer table.

Since 4 bytes are required to store the CS and IP values for each interrupt service procedure, the table can hold the starting addresses for 256 interrupt service routines.

All the 256 interrupt pointers are arranged in the memory table, each interrupt type is given a number between 0 to 255 and the address of each interrupt is found by multiplying the type by 4 .

E.g, for type 11, interrupt address is    l l x 4 = 44D= 0002CH

Only first five types have explicit definitions such as divide by zero and non maskable interrupt. The next 27 interrupt types, from 5 to 31, arc reserved by Intel for future use. The upper 224 interrupt types, from 32 to 255, are available for user for Hardware or software interrupts.