MPMC UNIT-1 General Bus Operation, Modes of operation 0f 8086

 

MICROPROCERSSORS AND   MICROCONTROLLERS      REGULATION /BRANCH :R16/R18  ECE/EEE

                                      UNIT-I

General Bus Operation:

The 8086 has a combined address and data bus commonly referred as a time multiplexed address and data bus.

    The main reason behind multiplexing address and data over the same pins is the maximum utilization of processor pins and it facilitates the use of 40 pin standard DIP package. The bus can be demultiplexed using a few latches and transreceivers, when ever required.

Basically, all the processor bus cycles consist of at least four clock cycles. These are referred to as T1, T2, T3, T4. The address is transmitted by the processor during T1. It is present on the bus only for one cycle.

The negative edge of this ALE pulse is used to separate the address and the data or status information. In maximum mode, the status lines S0, S1 and S2 are used to indicate the type of operation. Status bits S3 to S7 are multiplexed with higher order address bits and the BHE signal. Address is valid during T1 while status bits S3 to S7 are valid during T2 through T4.

Deriving System Bus

 The 8086 has a multiplexed 16-bit address / data bus (AD0 - AD15 ) and a multiplexed     4-bit address /status bus A16/S3 - A19/ S6. The address can be latched using signal ALE.

     Commercially available latch chips contain eight latches. Thus for demultiplexing twenty address lines one requires three latch chips like 74373. While de-multiplexing the address bus, two of the three latch chips will be fully used and four latches of the third chip will be used. Figure 1.10 shows arrangement for latching the twenty bit address. Di indicate D inputs of latches and Q indicate the respective latch outputs.

Deriving Address Bus

Ø  8086 has a 16-bit multiplexed address and data bus(AD0-AD15) and a 4-bit multiplexed       Address and Status bus(A16/S3 to A19/S6).
Ø  The main reason behind multiplexing address and data over the same pins is the                      maximum utilization of processor pins.
Ø  The bus can be demultiplexed using a few latches and transceivers, when ever required.

Ø  Basically, a processor bus cycle consist of at least four clock cycles (T1, T2, T3 &T4).

       The address is transmitted (latched using ALE) by the processor during T1.

       Data is available during T2 through T4

Deriving Data Bus

8086 has multiplexed 16-bit data bus in the form of AD0 – AD15 . The data can be separated from the address and buffered using two bidirectional buffers 74245. It may be noted that the data can either be transferred from microprocessor to memory or from memory to microprocessor in case of write or read operations respectively hence bidirectional buffers are required for deriving the data bus. The signals DEN and DT / R indicate the presence of data on the bus arid the direction of the data, i.e. to / from the microprocessor They are used to drive the chip select (enable) and direction pins of the buffers.

If DEN is low it indicates that the data is available on the multiplexed bus and both the buffers (74245) are enabled to transfer data. When DIR pin goes high the data available at X pins of 74245 are transferred to Y pins. i.e. data is transmitted from microprocessor to either memory or 10 device (write operation). If DIR pin goes low' the data available at Y pins of 74245 is transferred to X pins, i.e. data is received by microprocessor from memory or I/O device (read operation).

 Deriving Control Bus

For deriving control bus from the available control signals RD , WR and M / I0 in case of minimum mode of operation any combinational logic circuit may be used.In case of maximum mode of operation a bus controller chip derives all the control signals using status signals S0,S1,S2.

 MODES OF OPERATION OF 8086

v  The 8086 can be operated in two different modes; namely minimum mode and maximum mode.

v  MN / MX : Logic level at this pin decides whether the processor is to operate in either minimum/ maximum mode.

1. Minimum Mode 8086 System

Ø In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum mode by strapping its MN/MX pin to logic 1.

Ø In this mode, all the control signals are given out by the microprocessor chip itself.

Ø There is a single microprocessor in the minimum mode system.

Ø The remaining components in the system are latches, transceivers, clock generator, memory and I/O devices. Some type of chip selection logic may be required for selecting memory or I/O devices, depending upon the address map of the system.

Ø Latches are generally buffered output D-type flip-flops like 74LS373 or 8282. They are used for separating the valid address from the multiplexed address/data signals and are controlled by the ALE signal generated by 8086.

Ø Transceivers are the bidirectional buffers and sometimes they are called as data amplifiers. They are required to separate the valid data from the time multiplexed address/data signals.

Ø They are controlled by two signals namely, DEN and DT/R.

Ø The DEN signal indicates the direction of data, i.e. from or to the processor. The system contains memory for the monitor and users program storage.

Ø Usually, EPROM are used for monitor storage, while RAM for users program storage. A system may contain I/O devices.

Ø The working of the minimum mode configuration system can be better described in terms of the timing diagrams rather than qualitatively describing the operations.

Ø The opcode fetch and read cycles are similar. Hence the timing diagram can be categorized in two parts, the first is the timing diagram for read cycle and the second is the timing diagram for write cycle.

Read Cycle timing Diagram for Minimum Mode

Ø The read cycle begins in T1 with the assertion of address latch enable (ALE) signal and also M / IO signal. During the negative going edge of this signal, the valid address is latched on the local bus.

Ø The BHE and A0 signals address low, high or both bytes. From T1 to T4 , the M/IO signal indicates a memory or I/O operation.

Ø At T2, the address is removed from the local bus and is sent to the output. The bus is then tristate. The read (RD) control signal is also activated in T2.

Ø The read (RD) signal causes the address device to enable its data bus drivers. After RD goes low, the valid data is available on the data bus.

Ø The addressed device will drive the READY line high. When the processor returns the read signal to high level, the addressed device will again tristate its bus drivers.

Ø A write cycle also begins with the assertion of ALE and the emission of the address. The M/IO signal is again asserted to indicate a memory or I/O operation. In T2, after sending the address in T1, the processor sends the data to be written to the addressed location.

Ø The data remains on the bus until middle of T4 state. The WR becomes active at the beginning of T2 (unlike RD is somewhat delayed in T2 to provide time for floating).

Ø The BHE and A0 signals are used to select the proper byte or bytes of memory or I/O word to be read or write.

Write Cycle timing Diagram for Minimum Operation

 

2. Maximum Mode 8086 System

In the maximum mode, the 8086 is operated by strapping the MN/MX pin to ground.

Ø  In this mode, the processor derives the status signal S2, S1, S0. Another chip called bus controller derives the control signal using this status information.

Ø  In the maximum mode, there may be more than one microprocessor in the system configuration.

Ø  The components in the system are same as in the minimum mode system.

Ø  The basic function of the bus controller chip IC8288, is to derive control signals like RD and WR (for memory and I/O devices), DEN, DT/R, ALE etc. using the information by the processor on the status lines.

Ø  The bus controller chip has input lines S2, S1, S0 and CLK. These inputs to 8288 are driven by CPU.

Ø  It derives the outputs ALE, DEN, DT/R, MRDC, MWTC, AMWC, IORC, IOWC and AIOWC. The AEN, IOB and CEN pins are specially useful for multiprocessor systems.

Ø  INTA pin used to issue two interrupt acknowledge pulses to the interrupt controller or to an interrupting device.

Ø  IORC, IOWC are I/O read command and I/O write command signals respectively. These signals enable an IO interface to read or write the data from or to the address port.

Ø  The MRDC, MWTC are memory read command and memory write command signals respectively and may be used as memory read or write signals.

Ø  All these command signals instructs the memory to accept or send data from or to the bus.

Ø  For both of these write command signals, the advanced signals namely AIOWC and AMWTC are available.

Ø  Here the only difference between in timing diagram between minimum mode and maximum mode is the status signals used and the available control and advanced command signals.

READ CYCLE TIMING DIAGRAM IN MAXIMUM MODE

Ø  S0, S1, S2 are set at the beginning of bus cycle.8288 bus controller will output a pulse as on the ALE and apply a required signal to its DT / R pin during T1.

Ø  In T2, 8288 will set DEN=1 thus enabling transceivers, and for an input it will activate MRDC or IORC. These signals are activated until T4. For an output, the AMWC or AIOWC is activated from T2 to T4 and MWTC or IOWC is activated from T3 to T4.

Ø  The status bit S0 to S2 remains active until T3 & become passive during T3 and T 4.

Ø  If reader input is not activated before T3, wait state will be inserted between T3 &T4.

Ø  The request/grant response sequence contains a series of three pulses. The request/grant pins are checked at each rising pulse of clock input.

Ø  When a request is detected and if the condition for HOLD request is satisfied, the processor issues a grant pulse over the RQ/GT pin immediately during T4 (current) or T1 (next) state.

Ø  When the requesting master receives this pulse, it accepts the control of the bus, it sends a release pulse to the processor using RQ/GT pin

WRITE CYCLE TIMING DIAGRAM IN MAXIMUM MODE