MPMC UNIT-1 Architecture 0f 8086

 

MICROPROCERSSORS AND   MICROCONTROLLERS      REGULATION /BRANCH :R16/R18  ECE/EEE

                                      UNIT-I

ARCHITECTURE OF 8086

 

The complete architecture of 8086 can be divided into two parts

(a) Bus Interface Unit t BIU) - contains the circuit for physical address calculations and        a pre decoding  instruction byte queue (6 bytes long).

 (b) Execution Unit (EU)- executes instructions from the instruction  byte queue

BUS INTERFACE UNIT:

v The bus interface unit is responsible for establishing communications with external devices and peripherals including memory via the bus.

vBIU contains Instruction queue, Segment registers, Instruction pointer, Address adder. 

   EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register, Flag register.

vIt provides a full 16 bit bidirectional data bus and 20 bit address bus.

vSpecifically it has the following functions: Instruction fetch, Instruction queuing, Operand fetch and storage, Address relocation and Bus control.

vThe BIU uses a mechanism known as an instruction byte queue to implement a pipeline architecture.

vBIU pre-fetches the instructions and the pre-fetched instructions are held in its FIFO queue. With its 16 bit data bus, the BIU fetches two instruction bytes in a single memory cycle.

vAfter a byte is loaded at the input end of the queue, it automatically shifts up through the FIFO to the empty location nearest the output.

vThe EU accesses the queue from the output end. It reads one instruction byte after the other from the output of the queue.

vIf the BIU is already in the process of fetching an instruction when the EU request it to read or write operands from memory or I/O, the BIU first completes the instruction fetch bus cycle before initiating the operand read / write cycle.

vThe BIU also contains a dedicated adder which is used to generate the 20bit physical address that is output on the address bus. This address is formed by adding an appended 16 bit segment address and a 16 bit offset address.

For example: The physical address of the next instruction to be fetched is formed by combining the current contents of the code segment CS register and the current contents of the instruction pointer IP register.

vThe BIU is also responsible for generating bus control signals such as those for  memory read or write and I/O read or write.

vThe BIU performs all bus operations such as instruction fetching, reading and writing operands for memory and calculating the addresses of the memory operands. The instruction bytes are transferred to the instruction queue.

vBoth units operate asynchronously to give the 8086 an overlapping instruction fetch and execution mechanism which is called as Pipelining. This results in efficient use of the system bus and system performance.

EXECUTION UNIT

The execution unit contains the register set of 8086 except segment registers and IP. It has a 16-bit ALU, able to perform arithmetic and logic operations. The 16-bit flag register reflects the results of execution by the ALU. The decoding unit decodes the opcode bytes issued from the instruction byte queue. The timing and control unit derives the necessary control signals to execute the instruction opcode received from the queue, depending upon the information made available by the decoding circuit. The execution unit may pass the results to the bus interface unit for storing them in memory.

v  The Execution unit is responsible for decoding and executing all instructions.

v During the execution of the instruction, the EU tests the status and control flags and updates them based on the results of executing the instruction.   

v  If the queue is empty, the EU waits for the next instruction byte to be fetched and shifted to top of the queue.

v  When the EU executes a branch or jump instruction, it transfers control to a location corresponding to another set of sequential instructions.

v Whenever this happens, the BIU automatically resets the queue and then begins to fetch instructions from this new location to refill the queue.

 Instruction Queue

To speed up program execution, the BIU fetches six instruction bytes ahead of time from the memory. These pre fetched instruction bytes are held for the execution unit in a group of registers called Queue, With the help of queue it is possible to fetch next instruction when current instruction is in execution.

For example, current instruction in execution. During this execution time the BIU fetches the next instruction or instructions from memory into the instruction queue instead of remaining idle. The BIU continues this process as long as the queue is not full. Due to this, execution unit gets the ready instruction in the queue and instruction fetch time is eliminated.

The queue operates on the principle first in first out (FIFO). So that the execution unit gets the instructions for execution in the order they are fetched. In case of  JUMP/ CALL instructions, instruction already fetched in queue are of no use. Hence, in these  cases queue Ls dumped and newly formed by loading instructions from  new address specified by JUMP /CALL  instruction.

Feature of fetching the next instruction while the current instruction is executing is called pipelining.