MPMC UNIT-1 Memory Segmentation, Programming Model, Memory Address Generation, Physical Memory Organization

MICROPROCERSSORS AND   MICROCONTROLLERS      REGULATION /BRANCH :R16/R18  ECE/EEE

                                           UNIT-I

MEMORY SEGMENTATION 

Two types of memory organizations are commonly used.

LINEAR ADDRESSING - the entire memory space is available to the processor in one linear array.

SEGMENTED ADDRESSING - the available memory space is divided into "chunks" called segments. Such a memory is known as segmented memory.

The memory in an 8086/8088 based system is organized as segmented memory. In this scheme, the complete physically available memory may be divided into a number of logical segments. Each segment is 64K bytes in size and is addressed by one of the segment registers. The 16-bit contents of the segment  register actually point to the starting Location of a particular segment. To address a specific memory location within a segment, we need an offset address. The offset address is also 16-bit long so that the maximum offset value can be FFFFH, and the maximum size of any segment is thus 64K locations.

             The CPU 8086 is able to address 1 Mbytes of physical memory. The complete 1 Mbytes memory can be divided into 16 segments, each of 64Kbytes size. The addresses of the segments may be assigned as 0000H to F000H respectively. The offset address values are from 00000H to FFFFH so that the physical addresses range from (00000)H to FFFFFH.

 Rules for Memory Segmentation

1. The four segments can overlap for small programs. In a minimum system all four segments can start at the address 00000H.

2. The segment can start at any memory address which is divisible by 16.

3. Segment overlapping is allowed

Advantages of Memory Segmentation

v It allows the memory addressing capacity to be 1 MB  even though the actual addresses to be handled are of 16-bit size.

v It facilitates use of separate memory areas for program, data and stack.

v It allows placing of code, data and stack part of  the same program  in different segments of  the memory for code and data protection which is very useful in multiprogramming.

v The segment registers allows the code, data and stack to be more than 64 KB long.

     It can be achieved by using more than one code, data and stack segments.

 

PROGRAMMING MODEL OF 8086

 

Memory Address Generation

To address 1 MB Memory in 8086 memory addresses are 20 bit wide ranging from 00000H to FFFFFH. For generating a physical address from contents of the registers, the content of a segment register also called as segment address is shifted left bit-wise four times and to this result, content of an offset register also called as offset address is added, to produce a 20-bit physical address. 

For example, if the segment address is 1005H and the offset is 5555H, then the physical address is calculated as below:

      

        Segment address ------ > 1005H

        Offset address —-> 5555H

        Segment address ------- > 1005H----- ≫ 0001 0000 0000 0101

        Shifted by 4 bit positions-------- >0001 0000 0000 0101 0000

        Offset address                   ----- >          0101 0101 0101 0101

 

        Physical address                 ----- >0001 0101 0101 1010 0101

                                                         1     5      5     A     5

PHYSICAL MEMORY Organization

The instruction stream is fetched from memory as words and is addressed internally by the processor as necessary. In other words, if the processor fetches a word (consecutive two bytes) from memory, there are different possibilities, like:

1. Both the bytes may be data operands

2. Both the bytes may contain opcode bits

3. One of the bytes may be opcode while the other may he data

All the above possibilities are taken care of by the internal decoder circuit of the microprocessor.

While referring to word data, the BIU requires one or two memory cycles, depending upon whether the starting byte is located at an even or odd address. It is always better to locate the word data at an even address. To read or write a complete word from/to memory, if it is located at an even address, only one read or write cycle is required. If the word is located at an odd address, the first read or write cycle is required for accessing the lower byte while the second one is required for accessing the upper byte.

Thus, two bus cycles are required, if a word is located at an odd address. It should be kept in mind that while initializing the structures like stack they should be initialized at an even address for efficient operation.

In an 8086 based system, the 1Mbytes memory is physically organized as an odd bank and an even bank, each of 512 Kbytes, addressed in parallel by the processor. Byte data with an even address is transferred on D7 - D0 , while the byte data with an odd address is transferred on D₁₅- D8 bus lines.

8086 is a 16-bit microprocessor and hence can access two bytes of data in one memory or I/O read or write operation. To store 16-hit data, two successive memory locations are used and the lower byte of 16-bit data can be stored in the first memory location while the second byte is stored in the next location. In a sixteen bit read or write operation both of these bytes will be read or written in a single machine cycle.

All the lower bytes are stored at even addresses and all the higher bytes are stored at odd addresses. Thus, the lower 8-bit memory bank is called as even address bank and the upper 8-bit memory hank  is called as odd address bank. The complete memory map of 8086 system is thus divided into even and odd address memory banks.

The processor provides two enable signals, BHE and A0 for selection of either even or odd or both the banks. 

BHE	A0	Indication
0	0	WHOLE WORD(D0-D15)
0	1	Upper byte(D8-D15)/Odd
1	0	Lower byte(D0-D7)/Even
1	1	None

 The bus high enable signal is used to indicate the transfer of data over the higher order (D15~D8) data bus. It goes low for the data transfers over D7-D0 and is used to derive chip select signals of odd address memory bank or peripherals.

BHE is low during T1 for read, write and interrupt acknowledge cycles, whenever a byte is to be transferred on the higher byte of the data bus.