MPMC UNIT-1 Signal Description of 8086

MICROPROCERSSORS AND   MICROCONTROLLERS      REGULATION /BRANCH :R16/R18  ECE/EEE

                                      UNIT-I

 Signal Description of 8086

The Microprocessor 8086 is a 16-bit CPU available in different clock rates and packaged in a 40 pin CERDIP or plastic package.
It operates in two modes:         Minimum mode and Maximum mode 

The 8086 operates in single processor(min) or multiprocessor configuration(max)  to achieve high performance. The pins serve a particular function in minimum mode (single processor mode) and other function in maximum mode configuration (multiprocessor mode).

The 8086 signals can be categorized in three groups.

1) Signal having common functions in minimum as well as maximum mode.

2) Signals which have special functions for minimum mode and

3) Signals having special functions for maximum mode.

 The following signal descriptions are common for both modes.

 AD15-AD0:  

These are the time multiplexed memory I/O address and data lines. Address remains on the lines during T1 state, while the data is available on the data bus during T2, T3, Tw and T4. These lines are active high and float to a tristate during interrupt acknowledge and local bus hold acknowledge cycles

A19/S6,A18/S5,A17/S4,A16/S3:

These are the time multiplexed address and status lines.

During T1 these are the most significant address lines for memory operations.   

During I/O operations, these lines are low.

During memory or I/O operations, status information is available on those lines for

T2,T3,Tw and T4.

The status of the interrupt enable flag bit is updated at the beginning of each clock cycle. The S4 and S3  indicate which segment register is presently being used for memory accesses.

These lines float to tri-state off during the local bus hold acknowledge.

The status line S6 is always low.

The address bit are separated from the status bit using latches controlled by the ALE signal.

 

S4	S3	Segment register
0	0	Alternate Data
0	1	SS
1	0	CS
1	1	DS

BHE /S7: The bus high enable is used to indicate the transfer of data over the higher order (D15-D8) data bus as shown in table. It goes low for the data transfer over D15-D8 and is used to derive chip selects of odd address memory bank or peripherals. BHE is low during T1 for read, write and interrupt acknowledge cycles, whenever a byte is to be transferred on higher byte of data bus. The status information is available during T2, T3 and T4. The signal is active low and tristate during hold. It is low during T1 for the first pulse of the interrupt acknowledges cycle. 

BHE	A0	Indication
0	0	WHOLE WORD(D0-D15)
0	1	Upper byte(D8-D15)/Odd
1	0	Lower byte(D0-D7)/Even
1	1	None

RD Read: This signal on low indicates the peripheral that the processor is performing s memory or I/O read operation. RD is active low and shows the state for T2, T3, Tw of any read cycle. The signal remains tri-stated during the hold acknowledge.

READY: This is the acknowledgement from the slow device or memory that they have completed the data transfer. The signal made available by the devices is synchronized by the 8284A clock generator to provide ready input to the 8086 .The signal is active high.

INTR-Interrupt Request: This is a triggered input. This is sampled during the last clock cycles of each instruction to determine the availability of the request. If any interrupt request is pending, the processor enters the interrupt acknowledge cycle.

This can be internally masked by resetting the interrupt enable flag. This signal is active

 high and internally synchronized.

TEST: This input is examined by a ‘WAIT’ instruction. If the TEST pin goes low, execution will continue, else the processor remains in an idle state. The input is synchronized internally during each clock cycle on leading edge of clock.

NMI-Non-maskable Interrupt This is an edge-triggered input which causes a Type2 interrupt.

The NMI is not maskable internally by software. A transition from low to high initiates the interrupt response at the end of the current instruction. This input is internally synchronized.

 RESET: This input causes the processor to terminate the current activity and start execution from FFFFOH. The signal is active high and must be active for at least four clock cycles. It restarts execution when the RESET returns low. RESET is also internally synchronized.

CLK-Clock Input: The clock input provides the basic timing for processor operation and bus control activity. It's an asymmetric square wave with 33% duty cycle. The range of frequency for different 8086 versions is from 5MHz to 10MHz.

Vcc :+5V power supply for the operation of the internal circuit.

GND :ground for the internal circuit.

MN/ MX : The logic level at this pin decides whether the processor is to operate in either minimum or maximum mode. 

The following pin functions are for the minimum mode operation of 8086.

M/ IO – Memory/IO: This is a status line logically equivalent to S2 in maximum mode. When it is low, it indicates the CPU is having an I/O operation, and when it is high, it indicates that the CPU is having a memory operation. This line becomes active high in the previous T4 and remains active till final T4 of the current cycle. It is tri stated during local bus “hold acknowledge “.

M/IO	RD	WR	Transfer type
0	0	1	IO Read
0	1	0	IO Write
1	0	1	Memory Read
1	1	0	Memory Write

INTA Interrupt Acknowledge: This signal is used as a read strobe for interrupt acknowledge cycles. In other words, when it goes low, it means that the processor has accepted the interrupt. It is active low during T2,T3 and Tw of each interrupt acknowledge cycle.

ALE – Address Latch Enable: This output signal indicates the availability of the valid address on the address/data lines, and is connected to latch enable input of latches. This signal is active high and is never tri stated.

DT/ R Data Transmit/Receive: This output is used to decide the direction of data flow through the transceivers (bidirectional buffers). When the processor sends out data, this signal is high and when the processor is receiving data, this signal is low. Logically, this is equivalent to S1 in maximum mode.

It’s timing is same as M/I/O. This is tri stated during ‘hold acknowledge

DEN – Data Enable: This signal indicates the availability of valid data over the address/data lines. It is used to enable the transceivers (bidirectional buffers) to separate the data from the multiplexed address/data signal. It is active from the middle of T2 until the middle of T4. This is tri stated during ‘hold acknowledge’ cycle.

HOLD, HLDA- Acknowledge: When the HOLD line goes high, it indicates to the processor that another master is requesting the bus access.

The processor, after receiving the HOLD request, issues the hold acknowledge signal on HLDA pin, in the middle of the next clock cycle after completing the current bus cycle. At the same time, the processor floats the local bus and control lines. When the processor detects the HOLD line low, it lowers the HLDA signal. HOLD is an asynchronous input, and is should be externally synchronized.

If the DMA request is made while the CPU is performing a memory or I/O cycle, it will release the local bus during T4 provided:

 

1. The request occurs on or before T2 state of the current cycle.

2. The current cycle is not operating over the lower byte of a word.

3. The current cycle is not the first acknowledge of an interrupt acknowledge sequence.

4. A Lock instruction is not being executed.

The following pin function are applicable for maximum mode operation of 8086.

S2, S1, S0 – Status Lines: These are the status lines which reflect the type of operation, being carried out by the processor. These become activity during T4 of the previous cycle and active during T1 and T2 of the current bus cycles.

The status lines return to passive state during T3 of the current bus cycle so that they may again become active for the next bus cycle during T4. 

S2	S1	S0	Indication
0	0	0	Interrupt Acknowledge
0	0	1	Read I/O port
0	1	0	Write I/O port
0	1	1	Halt
1	0	0	Code Access
1	0	1	Read memory
1	1	0	Write memory
1	1	1	Passive

LOCK This output pin indicates that other system bus master will be prevented from gaining the system bus, while the LOCK signal is low.

The LOCK signal is activated by the ‘LOCK’ prefix instruction and remains active until the completion of the next instruction. When the CPU is executing a critical instruction which requires the system bus, the LOCK prefix instruction ensures that other processors connected in the system will not gain the control of the bus.

The 8086, while executing the prefixed instruction, asserts the bus lock signal output, which may be connected to an external bus controller.

QS₁, QS₀ – Queue Status: These lines give information about the status of the code-

prefetch queue. These are active during the CLK cycle after while the queue operation is performed.

The 8086 architecture has 6-byte instruction pre-fetch queue. Thus even the largest (6 - bytes) instruction can be pr-fetched from the memory and stored in the pre fetch queue. This results in a faster execution of the instructions.

By pre-fetching the instruction, there is a considerable speeding up in instruction execution in 8086. This is known as instruction pipelining. 

QS1	QS0	Indication
0	0	None
0	1	First byte of opcode from the queue
1	0	Empty Queue
1	1	Subsequent byte from the queue

While the execution unit is busy in executing an instruction, after it is completely decoded, the bus interface unit may fetch the bytes of the next instruction from memory, depending upon the queue status.

RQ / GT0 , RQ / GT1 – Request/Grant: These pins are used by the other local bus master in maximum mode, to force the processor to release the local bus at the end of the processor current bus cycle.

Each of the pin is bidirectional with RQ/GT0 having higher priority than RQ/GT1.

Request/Grant sequence is as follows:

1. A pulse of one clock wide from another bus master requests the bus access to 8086.
2. During T4(current) or T1(next) clock cycle, a pulse one clock wide from 8086 to the requesting master, indicates that the 8086 has allowed the local bus to float and that it will enter the ‘hold acknowledge’ state at next cycle. The CPU bus interface unit is likely to be disconnected from the local bus of the system.
3. A one clock wide pulse from the another master indicates to the 8086 that the hold request is about to end and the 8086 may regain control of the local bus at the next clock cycle.

 Thus each master to master exchange of the local bus is a sequence of 3 pulses. There must be at least one dead clock cycle after each bus exchange. •The request and grant pulses are active low.

For the bus request those are received while 8086 is performing memory or I/O cycle, the granting of the bus is governed by the rules as in case of HOLD and HLDA in minimum mode.